Radiation-resistant elements design methodology for CAD of the electronic-components base of a “system-on-chip” type
Аuthors1*, 2**, 1***
1. Scientific Research Institute of System Analysis, 36/1, Nakhimovsky av., Moscow, 117218, Russia
At present, a crucially important problem consists in implementation of CMOS VLSI design, executed with the sub-micron «silicon on insulator» technology (SOI) in the dual-use equipment for of various management and control spaceborn systems, nuclear power and of many other facilities design. The priority here is the development of the of the base elements design of a CMOS LSI dual-use, which include both elementary logic gates, and other types of functional units. The solution to such problems now is impossible without creation of appropriate software tools and methodology of their aggregation and use in a single cycle of electronic-component base functional blocks models development. The article presents already tested designing route of standard CMOS-SOI elements library with minimal topological size of 0.25 microns, ensuring a guaranteed level of radiation resistance. It demonstrates the of software route, implementing the presented route and shows its practical realization on a concrete example. The process of the individual library element design (buffer) using CAD-systems is described in detail in a step-by-step manner. Practical value of the work consists in the fact that the output data formats are presented on each stage of the design. Besides, graphic illustration of the results of design on each step are presented.
Keywords:design route, library of standard elements, radiation resistance, Very Large Scale Integration, computer-aided design system
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