Global tracing method of the matrix large integrated circuits

Radio engineering


Nazarov A. V.



Goal: It is known that the quality of the final stage of matrix large-scale integrated circuits (LSI) design automation (the local routing stage) is determined by the efficiency of forming the large integrated circuits channels netlist generated in the preliminary stage of global tracing. While the problems of local tracing are covered sufficiently by publications, the problems of LSIs global tracing are insufficiently covered. The existing publications on this matter are devoted primarily to multilayered LSIs tracing. The paper proposes LSI global tracing with essentially limited pathways.

Design/Methodology/Approach. The paper presents the algorithm of the first phase of the creating conductors of a matrix LSI — the phase of global conductors tracing. This phase increases the efficiency of the successive stage of the tracing — the layout of interconnections of channels. The proposed algorithm is based on the Bellman-Kalaba method, which had been modified by introducing a system of penalties. This system of penalties allows taking into account the essntially limited resources for conductors tracing of the LSIs in the process of their synthesis.

Conclusions. According to the proposed method computer-based algorithm for LSI conductors tracing was developed. The paper presents the detailed description of the algorithm. Besides, it describes a system of penalties imposed on the new tracks, which take into account the previously created connections. This system of penalties is presented by formulas. The efficiency of the proposed algorithm is illustrated by the concrete example.

Practical implication. The algorithm implementation leads to reduction and balancing of separate channels loads. And, as consequence, tracing resources of the selected type of LSI are employed more efficiently.

Originality/Value. According to studies the suggested algorithm allows reducing the total area occupied by the LSI conductors approximately by 20–25 percent.


tracing, global tracing, design automation, gate array, algorithm, penalty function


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