Mathematical model of signal modulation type recognizing algorithm in the autocorrelation receiver for radio engineering monitoring means
DOI: 10.34759/trd-2020-113-09
Аuthors
*, **, ***Saint Petersburg Electrotechnical University “LETI”, 5, str. Professora Popova, Saint Petersburg, 197376, Russia
*e-mail: 10th20th30th@gmail.com
**e-mail: ap0d@ya.ru
***e-mail: leonov.vanya85@mail.ru
Abstract
The article presents a mathematical model development of the algorithm for recognizing the signal modulation type (linear-frequency modulation (LFM), phase-shift keying (PSK), and simple ones) in the autocorrelation receiver. Analysis of the algorithm implementation possibility on the FPGA basis is presented as well. Mathematical model adopts the assumption that the transfer gain of the autocorrelation receiver equals to one, and various distortionless filters pass the signal low-order components at the multipliers outputs. The article presents analytical description of the LFM, PSK simple signals processing in the autocorrelation receiver. Based on the developed model, the applicability boundaries of the algorithm were substantiated: 1.5 MHz bandwidth for the high-pass filter; up to 50 MHz for the bandwidth filters; and up to 100 KHz for low-pass filters. The time delay in the correlator of the autocorrelation receiver herewith lies within the 10 ns to 1000 ns range. Besides, based on the developed model, the effect of the delay time on the signal detection characteristics, which allows defining the optimal delay time for tuning the autocorrelation receiver while effective radar signals detection, was evaluated. Sequences of actions for analyzing the possibility of the developed model FPGA-based realization were proposed. The algorithm resource-intensity evaluation was performed. Evaluations of the resource-intensities of the filter system and spectrum obtaining devices, realized on the fast Fourier transform basis, were conducted. The evaluation result revealed that no less than 900 000 logic gates were required for the entire algorithm implementation. The appointed requirements are feasible for the majority of modern FPGAs, such as FPGA on the VU095 chip of the Virtex UltraScale family, which contains 1.176 million logic gates.
These requirements are true for most modern FPGAs. For example, it can be used the FPGA VU095 of the Virtex UltraScale family, which has 1.176 million logic gates.
Keywords:
modulation type recognition, autocorrelation receiver, FPGA, radio monitoringReferences
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