Processor load scheduling device in multiprocessor systems of critical purpose
DOI: 10.34759/trd-2020-115-14
Аuthors
1*, 1**, 1***, 2****1. South-Western State University, 94, 50-let Oktyabrya str., Kursk, 305040, Russia
2. Lavochkin Research and Production Association, NPO Lavochkin, 24, Leningradskay str., Khimki, Moscow region, 141400, Russia
*e-mail: borzovdb@mail.ru
**e-mail: r-basov@eureca.ru
***e-mail: titov-kstu@rambler.ru
****e-mail: jv.sokolova@mail.ru
Abstract
The need to prompt response from the computing system side emerges in the state-of-the-art multiprocessor critical systems. The systems, which failures lead to the losses (economic, physical, human etc.) are defined as critical systems. In the event of failure, such systems are the subject to high requirements for operability, reliability, safety, security, etc. All costs herewith associated with introduction of changes to such system or its replacing (direct, indirect, etc.) are more important that the losses occurred in the case of the multiprocessor system failure itself. It is obvious that minimization of both time and hardware costs, necessary for the multiprocessor system response to the hazardous situation is of most importance.
The failures occurring in the internal processor modules, such as aircraft cockpits, surveillance systems, targeting, atomic systems etc., can be assigned to the critical situations. In case of the multiprocessor system failure herewith, its performance and response decrease, which is unacceptable in critical systems. One of the options for this issue solving may be processor loading planning in multiprocessor systems. In this case, the multiple loading of several processors by the same task (routine, subroutine, algorithm, file, etc.) can be avoided, and, with this, the queue of the incoming tasks can be planned in such a fashion that they are being fed simultaneously. This allows reduce unplanned operation downtime and, at the same, time increase its availability factor along with increased performance.
The presented work is devoted to critical multiprocessor systems, to which high availability objects, which operability is critical for any kind of activity, can be assigned. In such cases, a person, country, enterprise, organization, etc. is distinguished. A failure in this case leads to in the system response time decrease and a further decrease in its performance, and, thus, the availability. In this case, the application of the software for solving this issue is unacceptable, which means that it is necessary to use specialized hardware load scheduling tools.
Keywords:
multiprocessor system, scheduling, loading, high availability, assignment, method, algorithm, scheduleReferences
-
Tsil’ker B.Ya. Organizatsiya EVM i system (Organization of computers and systems), Saint Petersburg, Piter, 2007, 668 p.
-
Ore O. Teoriya grafov (Theory of Graphs), Moscow, Nauka, 1968, 352 p.
-
Kormen T.M. et al. Algoritmy: postroenie i analiz. Algoritmy dlya raboty s grafami (Algorithms: construction and analysis. Algorithms for working with graphs), Saint Petersburg, Izdatel’skii dom “Vil’yams”, 2006, 1296 p.
-
Stallings W. Computer organization and architecture. Designing for Perfomance. Tenth Edition, Prentice-Hall, 1999. URL: http://home.ustc.edu.cn/~leedsong/reference_books_tools/Computer%20Organization%20and%20Architecture%2010th%20-%20William%20Stallings.pdf
-
Levin I.I., Shteinberg B.Ya. Iskusstvennyi intellect, 2001, no. 3, pp. 234 – 242.
-
Slyusar V. Elektronika NTB, 2007, no. 1. URL: https://www.electronics.ru/journal/article/514
-
Maiorov S.A., Kirillov V.V., Pribluda A.A. Vvedenie v mikroEVM (Introduction to microcomputers), Leningrad, Mashinostroenie, 1988, 304 p.
-
Mikushin A.V., Sazhnev A.M., Sedinin V.I. Tsifrovye ustroistva i mikroprotsessory (Digital devices and microprocessors), Saint Petersburg, BKhV-Peterburg, 2010, 832 p.
-
Busurin V.I., Medvedev V.M., Karabitskii A.S., Groppa D.V. Trudy MAI, 2017, no. 97. URL: http://trudymai.ru/eng/published.php?ID=87277
-
Basov R.G., Borzov D.B., Loktionova O.G. Svidetel’stvo o gosudarstvennoi registratsii programm na EVM № 2019616927 RF, 30.05.2019.
-
Basov R.G., Borzov D.B., Titov V.S. Telekommunikatsii, 2020, no. 1, pp. 41 – 48.
-
Trakhtengerts E.A. Vvedenie v teoriyu analiza i rasparallelivaniya programm EVM v protsesse translyatsii (Introduction to the theory of analysis and parallelization of computer programs in the translation process), Moscow, Nauka, 1981, 254 p.
-
Tyutlyaeva E.O., Konyukhov S.S., Odintsov I.O., Moskovsky A.A. Seismic Processing Performance Analysis on Different Hardware Environment, Seismic Processing Performance Analysis on Different Hardware Environment, 2017, vol. 4, no. 3, pp. 80 – 90. DOI: 10.14529/jsfi170305
-
Khokni R., Dzhesskhoup K. Parallel’nye EVM. Arkhitektura, programmirovanie i algoritmy (Parallel computers. Architecture, programming and algorithms), Moscow, Radio i svyaz’, 1986, 392 p.
-
Kalyaev A.B., Levin I.I. Modul’no-narashchivaemye mnogoprotsessornye sistemy so strukturno-protsedurnoi organizatsiei vychislenii (Modularly expandable multiprocessor systems with structural and procedural organization of computations), Moscow, Yanus-K, 2003, 379 p.
-
Borzov D.B., Chernetskaya I.E. Proektirovanie protsessora EVM (Computer processor design), Kursk, Izd-vo Yugo-Zapadnyi gosudarstvennyi universitet, 2020, 199 p.
-
Momose S. SX-Aurora TSUBASA. Brand-new Vector Supercomputer, SC’17 Supercomputer Forum, 2017. URL: https://www.osp.ru/os/2018/01/13053934
-
Kuz’minskii M. Otkrytye sistemy SUBD, 2016, no. 3, pp. 4 – 6. URL: https://www.osp.ru/os/2016/03/13050252
-
Markaryan A.O., Churkov I.S. Trudy MAI, 2020, no. 113. URL: http://trudymai.ru/eng/published.php?ID=118150. DOI: 10.34759/trd-2020-113-10
- Nabatov A.N., Vedenyapin I.E., Mukhtarov A.R. Trudy MAI, 2018, no. 102. URL: http://trudymai.ru/eng/published.php?ID=99177
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