Design of an integrated circuit topology for an algebraic convolutional codec

Аuthors

Volkov A. S.^*, Solodkov A. V.^**

National Research University of Electronic Technology, Bld. 1, Shokin Square, Zelenograd, Moscow, Russia, 124498

*e-mail: leshvol@mail.ru
**e-mail: solodkov_aw@mail.ru

Abstract

Modern telecommunication systems and communication networks development is being accompanied by a permanent growth of the transmitted messages volume and speed. High demands are placed herewith on the transmitted information reliability, both in wired and wireless systems. The problem solution to the of transmitted information reliability increasing is the error-correcting convolutional coding and decoding methods application. At the same time, Russian telecommunications companies are showing interest in domestic developments in microelectronics to ensure target indicators of domestic communication systems noise immunity.

The purpose of this article consists in the topology designing of an integrated circuit for codec of algebraic convolutional (n, k)-code. The work was funded by the Ministry of Education and Science of Russia within the framework of Federal project “Training of personnel and scientific foundation for the electronics industry” according to the State assignment for the implementation of research work “Development of the Technique for Electronic Component Base Prototyping with Domestic Microelectronic Production based on the MPW Service (FSMR-2023-0008)”.

The authors considered a coding algorithm, defining a convolutional code in a polynomial manner through a set of generating polynomials. This approach allows determining the convolutional code parameters at the design stage. Two decoding algorithms have been proposed: the Viterbi algorithm and the algebraic decoding algorithm.

The integrated circuit topology of the algebraic convolutional codec has been designed, and its main parameters description has been performed. These parameters are as follows: the number of chip contacts is 52; the size is 20 х 20 microns; maximum operating frequency is up to 250 MHz, and peak consumption is of no more than 200 mA.

The integrated circuit of the algebraic convolutional codec allows both algebraic decoding at the length of the code word section and Viterbi decoding applying soft decision metrics.

As the result of modeling, the following values of the E_b/N₀ ratio for bit error probability of q_bit = 10^–3 were obtained: 5.68 dB at R ≈ 2/3 and 6.12 dB at R ≈ 1/2 and 6.91 dB at R ≈ 1/3. The obtained values for the E_b/N₀ ratio for the bit error probability q_bit = 10^–6 corresponds to the following values: .23 dB at R ≈ 2/3; 8.41 dB at R ≈ 1/2 and 9.18 dB at R ≈ 1/3.

Keywords:

convolutional codes, construction of convolutional codes, decoding of convolutional codes, codec integrated circuit, codec topology, error-correction codes

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