Evaluating buffer memory organization impact on the message source detection procedures speed
DOI: 10.34759/trd-2020-114-15
Аuthors
*, **, ***South-Western State University, 94, 50-let Oktyabrya str., Kursk, 305040, Russia
*e-mail: tanygin@yandex.ru
**e-mail: haideryhy7@gmail.com
***e-mail: dobritsa@mail.ru
Abstract
Rather strict requirements to the control cycle duration are being laid in certain types of information systems, such as mobile objects control systems, robotic systems and other real-time systems. Thus, the bit capacity reduction problem of messages transmitted between controlling, monitoring, switching and executing devices is urgent for them. One of the approaches to this is size reduction of the additional service information fields, intended for data integrity and authenticity control. The purpose of the work consists in obtaining numerical dependencies between the required buffer memory volume of the receiver and the execution speed increasing of analysis operations, as well as determining conditions of the memory organization option, being under consideration, application.
The authors established the relationships between the probability error value of the data placing in the receiver buffer and the number of interacting devices, the buffer memory size, and the length of the fragmented message. The article demonstrates that with buffer memory organized as isolated areas, the speed of memory attribute analysis increases proportionally to the length of the fragmented message transmitted between the source and receiver.
The article shows that with a small number of interacting devices, buffering messages from various sources in isolated memory areas can increase the speed of analysis of attribute information by a factor determined by the fragmented message length. The ratios between the buffer size and the interacting devices number were determined, which reduced the probability of errors in data placement in the buffer up to a value not exceeding 0.1.
Keywords:
data processing, message receiver, RAM, performance, simulationReferences
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