The Analysis of Bit Sequence Redundancy for the Project Based on Field Programmable Gate Arrays

Аuthors

Pankratov A. V.^*, Yakimov V. L.^**, Makovskij V. N.^***

Mlitary spaсe Aсademy named after A.F. Mozhaisky, Saint Petersburg, Russia

*e-mail: pankratov-av@rambler.ru
**e-mail: yakim78@yandex.ru
***e-mail: sla_mvn777@mail.ru

Abstract

FPGA (Field Programmable Gate Arrays) are powerful tool for rapid development and can replace specialized chips of high performance of ASIC (Application Specific Integrated Circuit). The configuration of FPGA can be updated remotely, using the Internet. It makes does FPGA more attractive than ASIC. The configuring bit sequence of FPGA is stored in an external bulk non-volatile memory and transferred to internal static memory after switching on the device. It contains the complete information about a functionality of FPGA, operation modes of input/output ports, coordinations and communications of all used components. In the article the mechanism of conversion of device description in language of the high level in the configuring bit sequence which is written in the external bulk non-volatile memory of FPGA is considered. On the basis of the analysis of the considered conversion the families of bit flows corresponding to the given schematic diagram are selected. As an example unremovable redundance of a bit flow for switching node of a programmable array of connections is considered. The programmable array of connections is responsible for all communications between logic blocks of FPGA. Switching in a node of a matrix is carried out by field transistors, and each connection is controlled by one bit of the configuring bit sequence. Redundance of the configuring bit sequence is defined by number of possible options of switching and number of the involved bits of the configuring sequence. For xc3s1200e chip redundance makes about 35%. It is offered to consider possibility of assembly algorithms implementation of the project on FPGA using the model considering redundance.

Keywords:

FPGA bit stream, switching matrix

References

1. Xilinx DS312 Spartan-3E FPGA Family Data Sheet. http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf

2. Kuzelin M. O. Sovremennye semeistva PLIS firmy Xilinx (Modern FPGA Families from Xilinx), Moscow, Goriachaia liniia-Telekom, 2004, 440 p.

3. Maltsev G. N., Pankratov A. V., Makunin A. A. Informatsionno-upravlyayushchie sistemy, 2014, no. 6 (73), pp. 94–101.

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