Comparative analysis of test systems for FPGAS and their environment


DOI: 10.34759/trd-2022-125-22

Аuthors

Brekhov O. M.*, Ratnikov M. O.**

Moscow Aviation Institute (National Research University), 4, Volokolamskoe shosse, Moscow, А-80, GSP-3, 125993, Russia

*e-mail: obrekhov@mail.ru
**e-mail: m.o.ratnikov@mail.ru

Abstract

This work is devoted to the study and analysis of currently used FPGA test systems and their system environment, developed by both domestic and foreign researchers. More than 30 test systems based on the use of: built-in self-test structures (BIST), specially designed systems and systems that partially or completely use the target firmware are considered. The systems in question were used to solve various tasks: FPGA input control, testing of internal interconnection resources, testing of individual cells and embedded IP cores, testing of the FPGA system environment (external connections of FPGAs and the power subsystem), analysis of electrical, dynamic and functional characteristics in various conditions, search for single failures and failures. The systems used in the study of microcircuits for resistance to laser exposure, the flow of charged particles (including studies within the Alice CERN project and studies conducted by both FPGA suppliers and third-party researchers to compare the characteristics of various FPGAs), the accumulated dose of radiation, elevated temperature and changes in supply voltage are considered. The systems and methods that are used to debug the FPGA-based system are also considered. Also in the list of test systems considered there are systems used as a demonstrator of the application of methods for analyzing energy consumption, dynamic characteristics, reliability and fault tolerance, as well as testing and developing systems based on FPGAs. The result of the work is a classification of the considered systems, an analysis of the advantages and disadvantages of the considered systems and proposals for the further development of FPGA test systems and their system environment.

Keywords:

ASIC, FPGA, testing, test system, fault tolerance

References

  1. Matafonov D.E. Trudy MAI, 2018, no. 103. URL: https://trudymai.ru/eng/published.php?ID=100780
  2. Mullov K.D. Trudy MAI, 2016, no. 87. URL: https://trudymai.ru/eng/published.php?ID=69720
  3. Nicholas Wulf, Alan D. George, Ann Gordon-Ross. A Framework for Evaluating and Optimizing FPGA-Based SoCs for Aerospace Computing, ASM Transactions on Reconfigurable Technology Systems, 2016, vol. 10-1. DOI: 10.1145/2888400
  4. Cheynis B., Ducroux L., Grossiord J.-Y., Guichard A., Pillot P. et al. Radiation effects on V0 detector elements, Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2006, vol. 569, issue 3, pp. 732-736. DOI: 10.1016/j.nima.2006.09.086
  5. Andrea Alici, Antonioli P., Mati A., Meneghini S., Pieracci M. et al. Radiation tests of key components of the ALICE TOF Tdc Readout Module, Proceedings of 10th Workshop on Electronics for LHC Experiments and future Experiments, Boston, 13-17 September 2004.
  6. Jakub Podivinsky, Ondrej Cekan, Marcela Simkova, Zdenek Kotasek. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications, 2014 Proceeding of the 17th Euromicro Conference on Digital System Design, 2014, pp. 312-319. DOI: 10.1109/DSD.2014.57
  7. van Harten L.D., Mousavi M., Jordans R., Pourshaghaghi H.R. Determining the Necessity of Fault Tolerance Techniques in FPGA Devices for Space Missions, Microprocessors and Microsystems, 2018, no. 63, pp. 1-10. DOI: 10.1016/j.micpro.2018.08.001
  8. Abramovici M., Stroud C.E. BIST-Based Delay-Fault Testing in FPGAs, Journal of Electronic Testing, 2003, vol. 19, pp. 549–558. URL: https://doi.org/10.1023/A:1025126030727
  9. Alireza Sarvi, Carthik A. Sharma, Ronald F. DeMara. BIST-BASED Group Testing for Diagnosis of Embedded FPGA Cores, Proceedings of the 2008 International Conference on Embedded Systems & Applications, July 14-17 2008, Las Vegas, Nevada, USA.
  10. Latha M., Senthilmurugan M. Fault Detection and Fault Diagnosis in SRAM-Based FPGA Using BIST, Computer Science, Engineering, 2012, vol. 2, no. 4, pp. 609-614.
  11. Bradley F. Dutton, Charles E. Stroud. Built-In Self-Test of Configurable Logic Blocks in Virtex-5 FPGAs, 41st Southeastern Symposium on System Theory, 2009. DOI: 10.1109/SSST.2009.4806778
  12. Fazal Noorbasha, K. Harikishore, Ch. Hemanth, A. Sivasairam, V. Vijaya Raju. LFSR Test pattern for fault detection and diagnosis for FPGA clb cells, International Journal of Advances in Engineering & Technology, March 2012, vol. 3 (1), pp. 240-246.
  13. Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira. On-line Testing of FPGA Logic Blocks Using Active Replication, Norwegian Computer Science Conference (NIK’02), Kongsberg, Norway, November 2002, URL: https://www.researchgate.net/publication/228854731
  14. Ian G. Harris, Russell Tessier. Testing and Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Xplore, 2002, vol. 21(11), pp. 1337–1343. DOI: 10.1109/TCAD.2002.804108.
  15. J.L.V. Ramana Kumari, M. Asha Rani, N. Balaji, V. Sirisha. FPGA Implementation of Test Vector Monitoring BIST Architecture System, Conference paper «Microelectronics, Electromagnetics and Telecommunications», December 2016. DOI: 10.1007/978-81-322-2728-1_67.
  16. Akhmetov A.O., Sorokoumov G.S., Smolin A.A. et al. Proton Accelerator‟s Direct Ionization Single Event Upset Test Procedure, Proceedings IEEE 31st International Conference ON Microelectronics (MIEL), Niš, Serbia, September, 16-18, 2019, pp. 107-113.
  17. Yasuo Sato. In-Field Monitoring of Device Degradation for Predictive Maintenance. VLSI Design and Test for Systems Dependability, Springer Japan KK, 2019, pp 224.
  18. Hadi Jahanirad, Hanieh Karam. BIST-based Testing and Diagnosis of LUTs in SRAM-based FPGAs, Emerging Science Journal, 2017, vol. 1, no. 4, pp. 216-225.
  19. Mehdi Baradaran Tahoori. Application-Dependent Diagnosis of FPGAs, Proceeding of 2004 International Conference on Test, 2004. DOI: 10.1109/TEST.2004.1387002.
  20. Yong-Bo Liao, Ping Li, Ai-Wu Ruan, Yi-Wen Wang, Wen-Chang Li. A HW/SW Co-Verification Technique for FPGA Test, Journal of Electronic Science and Technology of China, 2009, vol. 1, no. 4, pp. 390-394.
  21. Chi-Feng Wu, Cheng-Wen Wu. Testing and Diagnosing Dynamic Reconfigurable FPGA, Computer Science, 2000, vol. 10, no. 3, pp. 321-333. DOI: 10.1155/2000/79281.
  22. Martin Rozkovec, Jiri Jenicheck, Zdenek Pliva. Using deterministic test vectors to test FPGA circuit, Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013. pp. 175-180.
  23. Zykav D., Kovrigin V. Komponenty i tekhnologii, 2004, no. 3 (38), pp. 168-170.
  24. Wang Zhongming, Yao Zhibin, Guo Hongxia, Lü Min. A software solution to estimate the SEU-induced soft error rate for systems implemented on SRAM-based FPGAs, Computer Science, 2011, vol. 32, no. 5, pp. 1-8. URL: https://doi.org/10.1088/1674-4926/32/5/055008
  25. Cinzia Bernardeschi, Luca Cassano and Andrea Domenici. Failure probability of SRAM-FPGA systems with Stochastic Activity Networks, Proceeding of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011. DOI: 10.1109/DDECS.2011.5783098.
  26. Menichelli, A. Papi, Jeffery Wyss. Ion beam testing of SRAM-based FPGA’s, 6th European Conference: Proce eding of the «Radiation and Its Effects on Components and Systems», 2001. DOI:10.1109/RADECS.2001.1159326
  27. Gregory R. Allen, Gary M Swift. Single Event Effects Test Results for Advanced Field Programmable Gate Arrays, 2006 IEEE Radiation Effects Data Workshop, 2006, pp. 115-120. DOI: 10.1109 REDW.2006.295478
  28. Niranjan Manoharan. Reliable and Fault-Resilient Schemes for Efficient Radix-4 Complex Division, Computer Science, 2014.
  29. Brian Pratt, Michael Caffrey, Paul Graham, Keith Morgan, Michael Wirthlin. Improving FPGA Design Robustness with Partial TMR, 2006 IEEE International Reliability Physics Symposium Proceedings, 2006, pp. 226-232. DOI: 10.1109/RELPHY.2006.251221.
  30. Bobrovskii D.V. Metody i sredstva prognozirovaniya stoikosti PLIS k vozdeistviyu radiatsionnykh faktorov kosmicheskogo prostranstva (Methods and means of prediction the FPGAs tolerance to the effects of space factors), Doctor’s thesis, Moscow, MIFI, 2011.
  31. Garcia, T. Gomes, F. Salgado, J. Cabral, P. Cardoso, M. Ekpanyapong, A. Tavares. A Fault Tolerant Design Methodology for a FPGA-based Softcore Processor, Proceedings of the 1st IFAC Conference on Embedded Systems, Computational Intelligence and Telematics in Control — CESCIT, Würzburg, Germany, 2012.
  32. A.B. Sanders, K.A. LaBel, C. Poivey, Joel A. Seely. Altera Stratix EP1S25 Field-Programmable Gate Array (FPGA), NASA/GSFC at 2005 MAPLD Conference, Washington, 2005, NASA, Washington DC, USA.
  33. Khalil Arshak, Essa Jafer, and Christian Ibala. Testing FPGA based digital system using XILINX ChipScopeTM logic analyzer, 29th International Spring Seminar on Electronics Technology, 2006, pp. 355-360. DOI: 10.1109/ISSE.2006.365129.
  34. Marcos T. Leipnitz, Gabriel L. Nazar, Fault Tolerance. Mechanisms for FPGA-Based Regular Expression Matching, Journal of Electronic Testing, 2018, vol. 34, pp. 487–506.
  35. Canivet G., Maistri P., Leveugle R. et al. Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA, Journal of Cryptology, 2011, vol. 24, no. 2, pp. 247–268.
  36. Osipenko P.N., Antonov A.A., Levadskii S.A. Programmnye produkty i sistemy, 2010, vol. 4, pp. 12-15.

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