A novel architecture for Field-Programmable Gate Array-based Ethernet POWERLINK controlled nodes

System analysis, control and data processing


Romanov A. M.

MIREA - Russian Technological University, 78, Vernadsky prospect, Moscow, 119454, Russia

e-mail: romanov@mirea.ru


The article solves the problem of Field-Programmable Gate Array (FPGA)-based Ethernet POWERLINK controlled node implementation with minimal application of both logical cells and memory blocks. As a solution, a novel modular architecture is proposed, which resource intensiveness can be flexibly adjusted depending on the required functionality. Unlike previously known solutions, the proposed architecture does not employ soft-processors and does not require the incoming frames buffering. All data is processed “on the fly”, which allows the node to send a response to the request from the managing node with the minimum latency allowable by the Ethernet standard. The novel architecture employs one shared kernel for interaction with the Ethernet physical layer chip (PHY). This kernel forms a common data channel to which all other modules are connected. Each module processes frames of a certain type (synchronous, asynchronous, cross-traffic frame) and generates corresponding responses. Based on the proposed architecture, the first Russian Ethernet POWERLINK device was created, which compliance with the Standard was certified by Ethernet POWERLINK Standardization Group. By the results of experimental studies, it was demonstrated that the novel architecture requires from 3.5 to 9 times less FPGA logic resources, and up to 126 times less block memory for the of Ethernet POWERLINK devices implementation. The result of no less importance is the possibility of proposed solutions implementation based on FPGA chips from Russian vendors, including those in radiation-resistant version, which allows apply them in aerospace technology.


fieldbus, field-programmable gate array, Ethernet POWERLINK, 61158 Standard, domestic element base


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